Generally, metal-oxide semiconductor transistors include a substrate made of a semiconductor material, such as silicon. The transistors typically include a source region, a channel/well region and a drain region within the substrate. The channel/well region is located between the source and the drain regions. A gate stack, which usually includes a conductive material, a doped poly Si, a gate oxide layer and sidewall spacers, is generally provided above the channel/well region. More particularly, the gate oxide layer is typically provided on the substrate over the channel region, while the gate conductor is usually provided above the gate oxide layer.
The amount of current flowing through a channel is generally directly proportional to the mobility of the carriers in the channel. Thus, by increasing the mobility of the carriers in the channel, the operation speed of the transistor can be increased. Also, mechanical stresses within a semiconductor device can modulate device performance by, for example, increasing the mobility of the carriers in the semiconductor device. Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive stresses are created in the channel of the n-type devices (e.g., NFETs) and/or p-type devices (e.g., PFETs). However, the same stress component, for example tensile stress or compressive stress, improves the device characteristics of one type of device (i.e., n-type device or p-type device) while discriminatively affecting the characteristics of the other type device. Also, some devices do not require tensile and/or compressive stresses in the substrate.
Also with the progress of CMOS scaling, the distance from source to drain is greatly shortened. Therefore the doping of source/drain and the LDD (lightly doped drain) have to be limited to prevent device punch through. This limitation requires source/drain and extension dose reduction, which will impact the device performance. Because of this, there is a need to keep the same doping level in the source/drain and extension but confine the dopant diffusion.
While known methods provide structures that have tensile stresses applied to the NFET device and compressive stresses applied along the longitudinal direction of the PFET device, they may require additional materials and/or more complex processing, and thus, resulting in higher cost. Thus, it is desired to provide more cost-effective and simplified methods for creating large tensile and compressive stresses in the channels NFETs and PFETs, respectively.